GitHub

LeEmperor/FPGAtors-SystemVerilog-Tutorial

These are the files used for the second presentation on SystemVerilog for FPGAtors club @ University of Florida. "vivado_proj.sh" in ./scripts will create a new vivado project taking in args ...
IEEE

FPGA Programming for Beginners: Bring your ideas to life by creating hardware designs and electronic circuits with SystemVerilog

Field Programmable Gate Arrays (FPGAs) have now become a core part of most modern electronic and computer systems. However, to implement your ideas in the real world, you need to get your head around ...
GitHub

OBI Bus Tutorial - Creating a Minimal OBI Master and Slave

This project provides a hands-on guide for creating and validating a minimal, OBI-compliant master and slave using simple SystemVerilog ports. All modules are tested against the official PULP OBI ...
Design-Reuse

SystemVerilog-VHDL-SystemC Verification IP Reuse Methodology

The growing complexity of SoCs and the reduced life cycle of electronic products demand higher levels of design productivity while meeting compressed development schedules. The reuse of design IP ...