GitHub

systolic_array_2x2.sv

input wire [DATA_WIDTH-1:0] a0, input wire [DATA_WIDTH-1:0] a1, output wire [2*DATA_WIDTH-1:0] c00, output wire [2*DATA_WIDTH-1:0] c01, output wire [2*DATA_WIDTH-1:0 ...
IEEE

Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs

Abstract: The last decade has witnessed the breakthrough of deep neural networks (DNNs) in various fields, e.g., image/speech recognition. With the increasing depth of DNNs, the number of ...
GitHub

quangdai-dai2k4/systolic-array-ip-dai

totnghiep/ ├── rtl/ │ ├── pe.v ← PE baseline (không zero-skip) │ ├── pe_lp.v ← PE low-power (có zero-skip) │ ├── systolic_array.v ← 8×8 array dùng pe.v │ ├── systolic_array_lp.v ← 8×8 array dùng pe_lp ...
IEEE

Novel FPGA based Systolic Array Design for Dynamic Workflows

Abstract: Convolutional neural network based object detection is an inevitable part of advanced driver assistance systems which has high accuracy and low latency requirements. Considering the high ...